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Preface

With the rapid rise of the 5G, artificial intelligence (AI), metaverse and other emerging technology industries developing chip architecture technology with low power consumption, small size, heterogeneous integration, and ultra-high computing speeds has become the most important key to success for global semiconductor manufacturers. Ever since INTEL introduced the innovative three-dimensional “fin transistor (FinFET)” on 22 nanometer devices in 2012, this architecture has served as the basis for research and development in the race for advanced wafer processes in the international semiconductor industry. The most current, state-of-the-art 5 nanometer process is made using the FinFET architecture. TSMC took the lead in this technology when it successfully moved into mass production in 2020.

However, in the future, when it comes time for processes to be scaled down to 3 nanometers, the FinFET architecture will have to face its physical limitations in leakage current control. In truth, Samsung has already jumped ahead by announcing the latest generation of new 3nm process architecture, which uses the Gate-All-Around FET (GAAFET). So, who will win the final showdown for leadership of the next generation of chip manufacturing? That still remains to be seen.

Compared to the FinFET, the GAAFET chip architecture has better power performance at a smaller size and can reduce the actual size of chips by 45% while simultaneously reducing energy consumption by 50%. TSMC intends to continue using the FinFET in this heated contest against Samsung’s GAAFET for supremacy in the field of 3nm advanced processes. 2022 will definitely be a crucial year for determining the victor. As for the much anticipated next generation 2nm technology node, TSMC has already publicly announced that it will also be using the GAAFET architecture. They plan to strengthen its competitive advantages in advanced processes by introducing low-dimensional, high electron mobility materials and special insulation materials, etc. The GAAFET architecture has apparently become the best option for the continued development of Moore’s Law in the next generation.

In this issue of the “New Technology Channel”, MA-Tek has specially invited Professor Chee Wee Liu, a top scholar in the field of advanced semiconductor processes, to write an article introducing the general situation and development trend of advanced transistor technology. We hope to share with our readers the progress that is being made in academic research in this important field of science and technology.

Director of R&D Center & Marketing Division, Chris Chen, 2022/01/20

The Soul of Electronic Components－Advanced Transistor Technology and Development Trends

Professor Chee-Wee Liu

Ph.D. students： Jhong-En Tsai, Yi-Jun Liu, Jian-De Du

Institute of Electronics Engineering, National Taiwan University

With the rapid advancement of technology, various electronic devices have become indispensable to our daily lives. All of these devices, from the large, like cars, to the small, like smartphones, have semiconductor chips at their cores. As such, semiconductor chips have also become inseparable from human life. Taiwan’s semiconductor industry has a crucial role to play in this world of technology. With the advent of the 5G era, which is facilitating the rapid development of big data, AI (artificial intelligence), the Internet of Things (IoT), and mobile smart devices, the demand for advanced semiconductors is and will continue growing. The efforts of various research teams to develop semiconductor process technology, along with government and corporate investments, have made the semiconductor industry both a pillar of support and an advantage for Taiwan’s future and growth.

The development of Moore’s Law led to the evolution from the μm technology node to today’s 5nm technology node (Figure 1) and the 3nm technology node expected to go into mass production in 2022[1]. The smaller the technology node, the higher the transistor density. In the past, two important technological breakthroughs were made during the development of Planar FET technology. One was the strained Si method that started the mass production of 90nm technology. It was able to improve the mobility of silicon channels and increase electrical currents. The second breakthrough was the development of the high-k/metal gate. The larger the k value of the dielectric layer, the larger the oxide capacitance (C_ox) and the higher the transistor current. In addition, under an equivalent oxide thickness (EOT), leakage current can be reduced with greater physical thickness.

Figure 1　TSMC’s Process Technology Nodes[1]

Figure 2　Rough Estimation of Technology Nodes and Gate Lengths

※ This diagram is copyrighted by Professor Chee Wee Liu of the Institute of Electrical Engineering at National Taiwan University and his research team. It may not be used, reproduced, or adapted in any form without permission.

As traditional semiconductors continue to be scaled down, the gate length of transistors is also gradually being reduced. However, the gate length and the size of the technology node are not equivalent. Once you move beyond the 22nm technology node, the gate length will be greater than the value of the technology node (Figure 2).

As transistors get smaller and smaller, traditional miniaturization techniques are reaching their physical limits. Scaling down based purely on Moore’s Law is no longer efficient. As such, the fin transistor (FinFET) proposed by Professor Zhengming Hu’s research team was adopted by the industry starting with the 22nm technology node (Intel) and 16nm technology node (TSMC). This three-dimensional transistor structure has become the mainstream of today’s advanced semiconductors.

Transistors are moving from the traditional planer structure (Figure 3a) to a three-dimensional structure (Figure 3b). Because this three-sided Tri-Gate structure is very similar in appearance to a fish’s fin, it has been dubbed the fin transistor. Fin transistors have a larger effective width than planer transistors, which means they can improve the current density of a device. In addition, its three-dimensional structure can improve channel controllability and suppress the short channel effect. The three-dimensional fin transistor structure also reduces subthreshold swing (SS) and operating voltage, thus reducing power loss (Figure 3c). Fin transistors have grown and contributed to the development of a total of five generations of technology nodes, from the 16nm, 10nm, and 7nm to the 5nm and 3nm nodes of mainstream components today.

Figure 3　(a) Planer Transistor Schematic, (b) Fin Transistor Schematic

TSMC announced its readiness to mass produce 5nm fin transistors with high mobility channels[3] at the 2019 International Electron Devices Meeting (IEDM). Using a high mobility channel is like driving a sports car. It is faster and has better performance. Figure 4[4] is the high mobility channel fin transistor shown by TSMC at the 2021 International Solid-State Circuits Conference (ISSCC). You can see in the figure that the high mobility channel clearly contrasts with the silicon material at the bottom and has a clear, dumbbell-like structure. TSMC expects to begin mass production of full-generation process transistors for the 3nm technology node in the second half of 2022. Moving from the 5nm to the 3nm node, the logic density will increase by approximately 70%, resulting in a 10 to 15% increase in speed under the same power consumption or 25 to 30% less power consumption at the same speed [1].

Figure 4　TSMC 5nm High Mobility Channel Fin Transistor[4] © IEEE

Changes must be made to the structure of the transistor in order to further increase the controllability of the channel while still suppressing the short channel effect. Samsung, TSMC, and Intel have announced that, for the 3nm technology node (Samsung) and the 2nm technology node (TSMC, Intel 20A), they will be using the Gate-All-Around (GAA) nanosheet structure. Gate-All-Around transistors have better gate control and allow for higher transistor density than fin transistors. As such, they will be replacing fin transistors in advanced technology nodes. Using the GAA transistor structure is just like using a powerful, well-designed faucet where the water does not leak. In other words, the transistor can effectively reduce the leakage current and thus save more energy. The drive current of the transistor can be increased using the channel stacking method, where you increase the number of channels in the vertical direction within the same area like you are building a double-deck bridge. This allows for more traffic. Similarly, stacking enables transistors to carry a higher current and increase transistor density, effectively improving component performance.

Figure 5 [5] shows the vertical stacked nanosheets structure. Think of FinFETs rotated 90 degrees and stacked vertically in a four-sided wrap-around gate structure. Unlike the FinFET, where the channel width (D_Fin) is limited by the Lithography process, the channel thickness (D_NS) of stacked nanosheets is determined by epitaxy, so thickness can be controlled with precision. In addition, stacked nanosheets can increase the number of channel layers vertically, meaning a greater effective width (W_eff) within the same footprint and a higher current, thus improving transistor performance. In addition to being able to accurately control the thickness of stacked nanosheets, epitaxy technology can control the distance between channels, a.k.a. suspension thickness (T_sus). So this approach does not increase the footprint the way the FinFET does, and it can reduce the parasitic capacitance of components by reducing T_sus.

Figure 5　Comparison of the IEEE of the FinFET and Stacked Nanosheets[5] © IEEE

Samsung took the lead in announcing at the 2018 IEDM international conference that it would be using GAA transistors with the Multi-Bridge-Channel FET (MBCFET) as the transistor structure for the 3nm technology node (Figure 6a, b) [6]. It was mentioned that the MBCFET adopts 90% of the FinFET process, meaning it has good compatibility with the FinFET processes of the current industry. The MBCFET, as its name suggests, is similar in structure to a multi-layer bridge. The structure is actually the same as that of the aforementioned stacked nanosheets. Compared to the FinFET, the MBCFET has better gate control. It also has a greater equivalent width within the same footprint to provide a greater drive current. Channel width can be adjusted to match different applications, increasing the flexibility of circuit design.

Figure 6　(a, b) Samsung’s 3nm Technology Node MBCFET[6] © IEEE

On the other hand, IBM’s 2nm technology node proposes the use of three vertically stacked nanosheets (Figure 6c) [5] with a channel width of 40nm, a channel height of 5nm, and a gate length of 12nm insulated with a bottom dielectric isolation (BDI) layer. This structure can effectively reduce leakage current and power consumption. In comparison to 7nm process technology, it is expected to improve performance by 45% while reducing power consumption by 75% [7].

TSMC showcased a three-layer vertically stacked nanosheets transistor structure for the 2nm technology node at the 2021 ISSCC international conference (Figure 7a). This structure would provide better performance and a lower subthreshold swing [4]. Intel has announced that it will be using the RibbonFET (vertically stacked four-layer nanoribbons similar in structure to stacked nanosheets) for the 20A technology node in 2024 (Figure 7b) [8]. They also plan to use the optimized RibbonFET as the structure for the 18A technology node in 2025. Furthermore, at the 2020 Symposium on VLSI Technology, VLSI, the French semiconductor research institute CEA-Leti proposed a seven-layer Si GAA nanosheets transistor (Figure 8) [9]. As you can see, it is clear from industry trends that GAA transistors with highly stacked channels will be the mainstream structure of future transistors.

Figure 7　(a) TSMC’s 2nm Three-Layer Vertically Stacked Channel Transistor[4] © IEEE

(b) Intel‘s Four-Layer Vertically Stacked Channel Transistor (RibbonFET) for the 20A Technology Node[8]

Figure 8　Seven-Layer Vertically Stacked Silicon Channel Transistor Published by CEA-Leti, a French Semiconductor Research Institute[9] © IEEE

Most of the GAA transistors published so far use silicon (Si) channel materials. To increase the operating speed of a circuit, the drive current (the sum of the vertically stacked channel currents) of the transistor must be boosted. In addition to increasing the number of channels in the vertical direction, the drive current of the transistor can also be improved by using materials with higher mobility for transistor channels. Materials such as germanium (Ge), germanium silicon (GeSi), germanium tin (GeSn), and other new group IV materials have better electron and hole mobility than silicon and have good compatibility with the current industry’s silicon semiconductor process technology.

Our research team presented an 8 stacked Ge_0.75Si_0.25 nanosheets N-type GAA transistor with a very high channel uniformity at the 2021 VLSI international conference (Figure 9 Left) [10]. In order to further increase the drive current, we increased the concentration of germanium in the germanium silicon channel to 95%, thus improving the electron mobility of the channel and successfully demonstrating the world’s first high-efficiency, 7 stacked Ge_0.95Si_0.05 nanowires N-type GAA transistor (Figure 9 Right) [10]. These research results were also reported as a Research Highlight in the top international journal Nature Electronics [11].

Figure 9　The 8 Layer GeSi Nanosheets (Left) and 7 Layer GeSi Nanowires (Right) Transistors Published by Our Research Team[10] © IEEE

It can be seen that high mobility channel GAA transistors with high-level stacks will be a major trend in future semiconductor technology nodes. Among the related process technologies, epitaxy and etching are the two most important when it comes to high-level stacked channel GAA transistors as high-efficiency transistors can be successfully prepared via the mutual optimization of the two. At present, NTU is the only institution outside the industry capable of developing multi-layer stacked channel GAA transistors. As such, it has become an important bridge between academia and the industry.

In terms of P-type transistors, because compressively strained germanium tin (GeSn) materials have higher hole mobility than pure germanium and silicon, it can be used to increase the drive current of a device. It has great potential as a channel material. However, due to the small energy gap of germanium tin materials, the device would have a larger off-state leakage current (I_OFF) and a smaller switch current ratio (I_ON/I_OFF), which would cause excessive power loss. This problem can be ameliorated by reducing the channel thickness. As the channel becomes thinner, the quantum confinement effect causes the I_ON/I_OFF to rise, and the subthreshold swing (SS) decreases due to enhanced gate control. However, when the channel thickness is less than 5nm, surface roughness scattering reduces mobility. Therefore, high stacking is required to maintain the drive current of the device when using germanium tin channels with high mobility.

As such, our research team proposed 7 stacked and 8 stacked Ge_0.9Sn_0.1 ultrathin bodies P-type transistors at the 2021 IEDM International conference (Figure 10) [12]. We used germanium tin materials for high mobility channels, by optimizing the epitaxy and highly selective isotropic dry etching (HiSIDE) processes, we achieved the fabrication of ultra-thin channels with a thickness of 3nm. This effectively reduced the leakage current of components and set a world record in the I_ON/I_OFF ratio of three-dimensional germanium/germanium tin transistors. This paper won the 2021 IEDM Best Student Paper Award. In summary, highly stacked, high mobility GAA transistors with ultrathin bodies will improve the performance of semiconductor chips while making them more power-saving. In this way, advanced semiconductor technology will continue to progress and improve the lives of mankind.

Figure 10　The 7 Layer (Left) and 8 Layer (Right) Germanium Tin Ultra-Thin Bodies Published by Our Research Team[12] © IEEE

References:

[1] TSMC [Online] https://www.tsmc.com/chinese/dedicatedFoundry/technology/logic

[2] M. Bohr and K. Mistry, “Intel’s Revolutionary 22 nm Transistor Technology,” [Online] https://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf

[3] G. Yeap et al., “5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021μm² SRAM cells for Mobile SoC and High Performance Computing Applications,” IEEE International Electron Devices Meeting (IEDM), pp. 879-882, 2019.

[4] Mark Liu, “Unleashing the Future of Innovation,” 2021 IEEE International Solid-State Circuits Conference (ISSCC), Plenary Session 1.1, 2021.

[5] N. Loubet, “Enablement of Next Generation High Performance Nanosheet Transistors,” IEEE International Electron Devices Meeting (IEDM), Short Course 1, 2020.

[6] G. Bae et al., “3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications,” IEEE International Electron Devices Meeting (IEDM), pp. 656-659, 2018.

[7] “IBM Unveils World's First 2 Nanometer Chip Technology, Opening a New Frontier for Semiconductors” [Online] https://newsroom.ibm.com/2021-05-06-IBM-Unveils-Worlds-First-2-Nanometer-Chip-Technology,-Opening-a-New-Frontier-for-Semiconductors

[8] “Intel Accelerated” [Online] https://download.intel.com/newsroom/2021/client-computing/Intel-Accelerated-2021-presentation.pdf

[9] S. Barraud et al., “7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing,” IEEE Symposia on VLSI Technology and Circuits (VLSI), TC1.2, 2020.

[10] Y.-C. Liu et al., “First Highly Stacked Ge_0.95Si_0.05 nGAAFETs with Record I_ON = 110 μA (4100 μA/μm) at V_OV=V_DS=0.5V and High G_m,max = 340 μS (13000 μS/μm) at V_DS=0.5V by Wet Etching,” IEEE Symposia on VLSI Technology and Circuits (VLSI), T15-2, 2021.

[11] S. Thomas, “Germanium nanowire transistors stack up,” Nature Electronics, Vol. 4, July 2021, 452.

[12] C.-E. Tsai et al., “Highly Stacked 8 Ge_0.9Sn_0.1 Nanosheet pFETs with Ultrathin Bodies (~3nm) and Thick Bodies (~30nm) Featuring the Respective Record I_ON/I_OFF of 1.4x10⁷ and Record I_ON of 92μA at V_OV=V_DS= -0.5V by CVD Epitaxy and Dry Etching,” IEEE International Electron Devices Meeting (IEDM), pp. 569-572, 2021.

Postscript

It has been more than forty years since the invention of the MOSFET structure. When gate length shrank below 20nm, we encountered many limitations due to the nature of physics, the two most representative being the Short-Channel Effect and the Quantum Tunneling Effect. With the development of FinFET technology, chip processes entered into the 5nm generation. Next, advanced process architecture will move from the FinFET to the GAAFET. When it does, TSMC, Samsung, and Intel are bound to meet in a fierce competition centered on the development of GAAFET technology at below 5nm.

However, though pursuing advantages in wafer manufacturing technology is important, in order to achieve technological leadership in the next era of semiconductor hegemony, we must also explore the development of system packaging and integration technology. The domestic industry, government, and academia should grasp this opportunity as soon as possible and work together to build a comprehensive strategy. Furthermore, it may be of interest to consider what innovations might come after the GAAFET generation. Will a new transistor structure capable of continuing the development of Moore’s Law emerges? We’ll just have to wait and see!

Professor Chee Wee Liu of National Taiwan University and his research team are the only domestic research team outside the industry capable of developing multi-layer stacked channel GAA transistors. Their work was published in top international journals in the semiconductor field in 2021. They successfully developed the world’s first GAA transistors with 7 layer and 8 layer stacked germanium silicon channels. MA-Tek is honored to be able to cooperate with Professor Liu on industry-university projects this year by providing all the analysis services required for GAAFET advanced process research. Ma-Tek has a complete set of testing equipment and professional technical experience to meet the various analysis and testing needs of advanced semiconductor processes and packaging. Click on the following links to learn more about related analysis technologies!

Plans for the next issue of the “New Technology Channel | Collaboration Column” are currently in progress, so stay tuned for more MA-tek technical articles. Become more competitive in the global supply chain by staying up to date on the most recent news on various cutting-edge technologies!

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