The Pursuit of High-Density Storage Applications－The Ferroelectric Memory

In recent years, the enormous amount of information analysis called for by emerging technologies such as artificial intelligence, the Internet of Things, 5G communications and smart vehicles has led the governments of many countries and numerous internationally renowned manufacturers such as Google, Apple, TSMC, Samsung, Intel, Toshiba, and SK Hynix to actively invest large amounts of resources into accelerating the development of next generation memory technology that can increase computing speeds and reduce power consumption. Among the emerging memory technologies, the most anticipated by the industry—the one believed to have the most potential to break through the bottleneck of the von Neumann architecture and become the foundation of the next stage of In-Memory Computing—is ferroelectric memory.

Today’s memory market is still dominated by DRAM and NAND Flash. Ferroelectric memory using HfO2 materials has not only a high polarization density that can greatly reduce the surface area of the memory cell but also good coating conformability that is beneficial to the construction of highly integrated 3D structures for semiconductor processes. Based on the progress of current research, ferroelectric memory may surpass NAND Flash in storage density and the maintenance of permanent memory and surpass DRAM in writing speed while having an endurance similar to that of DRAM. It is therefore reasonable to expect that, in the future, ferroelectric memory will be the key to the next generation memory technology that will bridge the boundary between DRAM and NAND Flash to realize storage-class memory and In-Memory Computing.

In this issue of the “New Technology Channel | Collaboration Column”, MA-tek has specially invited Professor Yung-Hsien Wu, a top scholar in the field of ferroelectric memory research, to write an article to introduce the current situation and development trends in ferroelectric memory technology as well as to share the progress being made in the academic research of this important field.

Director of R&D Center & Marketing Division, Chris Chen, 2022/02/20

The Pursuit of High-Density Storage Applications－The Principles, Challenges and Prospects of Ferroelectric Memory

Professor Yung-Hsien Wu 

Department of Engineering and Systems Science, National Tsing Hua University

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Data is the most important resource in today’s digital economy. Estimates made based on the popularity of mobile devices and the development of the Internet of Things (IOT) suggest that more than 2.5 quintillion (10¹⁸) bytes of data are being generated every day, and the rate at which this data is being generated continues to rise. Extensive computing resources are required to process such a huge amount of data, especially when the computers currently being used to perform calculations are based on the von Neumann architecture, where data must be transferred back and forth between the computing unit (CPU or GPU) and the memory. This not only limits the overall efficiency and computing time, which cannot meet real-time application needs, but also leads to astronomical energy consumption. The resulting limitation in data transfer efficiency is what we call the Memory Wall.

The term Memory-Centric mainly refers to technology that integrates both Near-Memory Computing and In-Memory Computing. Near-Memory Computing integrates computing chips and memory chips with die-level integration through advanced packaging technology. Another approach is to use a monolithic process for computing circuits and memory circuits and perform vertical device-level integration. The goal is to bring the data computing unit and the memory storage unit closer together, thus reducing transmission distance.

On the other hand, In-Memory Computing involves directly using the memory to complete the computational tasks of multiple neural networks of the Artificial Neural Network’s deep learning, including the Deep Neural Networks (DNN) and the Convolutional Deep Neural Network (CNN). This way, there would be no need to repeatedly transfer data between the computing unit and the memory. So, this approach could overcome the limitations of the von Neumann architecture and significantly improve computing performance. Taken a step further, it could enable the use of memory to realize the synapses of the nervous system. By applying axon and neuron behaviors to the new generation Spiking Neural Network (SNN), which is based on the human brain’s cognitive model, it would be possible to execute both computation and memory storage in the same place. This is also known as neuromorphic computing. It is a model for future computing architectures[1].

The core of the In-Memory Computing architecture is a memory element that has both computing and storage capabilities. Traditional NOR/NAND (Flash) memory and most emerging memory technologies like Resistive RAM (RRAM), Phase Change Memory (PCM), Magnetoresistive RAM (MRAM) and ferroelectric memory have the potential to realize In-Memory Computing or neuromorphic computing. Compared to other types of new-state memory, Ferroelectric memory has competitive advantages in terms of process compatibility and device performance. As such, it has attracted a great amount of attention from both academia and the industry in recent years.

Ferroelectric materials are materials capable of spontaneous polarization in the absence of an electric field. In other words, it is a material in which the positive/negative charge centers are separate, forming an electric dipole in a unit cell structure. In ferroelectric materials, the direction of the electric dipole of spontaneous polarization is not consistent. However, the spontaneous polarization direction of each unit cell within a specific area is the same. These regions are called ferroelectric domains.

Ferroelectric domains vary in polarization direction and strength and are distributed randomly throughout the material. As they cancel each other out, the overall ferroelectric material will appear to have no polarization. After applying an electric field to a ferroelectric material, however, the polarization direction of each ferroelectric domain will tend to become the same, and the material will reach saturation polarization (Ps). The electric dipole direction of the ferroelectric material can be changed when the electric field exceeds the positive coercive field (+Ec) or is lower than the negative coercive field (-Ec). When the applied electric field is removed, there will still be remanent polarization (Pr) in the ferroelectric material. This makes it very suitable for non-volatile memory devices. Figure 1 shows the relationship between the polarization and the applied electric field for a typical ferroelectric material.

Figure 1. Schematic Diagram of the Electric Field and Polarization of the Ferroelectric Layer

It has now been a hundred years since Rochelle Salt proposed ferroelectric materials in 1920. For half that century, scientists have been focused on traditional ferroelectric materials with a perovskite structure, such as BaTiO₃ (BTO) and Pb[Zr_xTi_1-x]O₃ (PZT). PZT in particular has been used in commercialized ferroelectric memory devices. However, the PZT ferroelectric material is not compatible with current integrated circuit processes. The Pb/O₂ diffusion phenomenon, the susceptibility of the material’s properties to being affected by H₂, and the difficulties of integrating the atomic layer deposition process all present barriers to mass production[2].

In addition, the ferroelectricity of perovskite films deteriorates rapidly when the thickness falls below a certain critical value. First-principles calculations predict that 6 unit cells is the critical value of ilmenite ferroelectric materials[3]. In other words, it has limits in terms of thickness miniaturization. This prevents the size of the memory from being scaled down. As a result, memory density cannot be effectively improved. Therefore, PZT-based ferroelectric memory devices occupy only a very small proportion of the semiconductor memory market.

It was first discovered in 2011 that HfO₂ doped with Si has ferroelectric properties[4]. These fluorite-structured oxides, such as doped HfO₂ and HfO₂/ZrO₂ solid solutions, have garnered a great deal of attention in both academia and the industry. The EU in particular has been extremely active in this regard. The Horizon 2020 plan supporting 3εFERRO Energy Efficient Embedded Non-volatile Memory & Logic based on Ferroelectric Hf(Zr)O₂ is a notable example of their efforts.

In order to continue developing high-speed, low-power and more reliable ferroelectric memory, it is necessary to explore more deeply the formation mechanism behind the HfO₂ ferroelectric layer. In truth, the ferroelectricity of HfO₂-based oxide layers is an extremely important discovery in the field of material science. This is because lab experiments and equilibrium phase diagram calculations both show that, under a stable thermal dynamic, HfO₂ is a centrosymmetric structure without ferroelectricity.

At room temperature, the most stable crystal phase of HfO₂ is the monoclinic crystal phase (P2₁/c, m-phase), which is converted to the tetragonal crystal phase (P4₂/nmc, t-phase) or cubic crystal phase (Fm3m, c-phase) after heating. While pressurized, a paraelectric/non-polar orthorhombic crystal phase (Pbca, Pmna) is formed. However, none of these crystal phases are ferroelectric. Through experiments and theoretical calculations, it has been found that ferroelectric HfO₂ is crystallized into a non-centrosymmetric/polar orthorhombic crystal (Pca2₁, o-phase)[5]. When an electric field is applied, the oxygen atoms in HfO₂ are displaced by the electric field, which is the so-called polarization[3].

How HfO2 forms the metastable crystal o-phase required for ferroelectricity is a hot research topic. After HfO2 undergoes phase transformation from a metastable crystal phase (such as t-phase) to the stable m-phase, it can no longer be transformed into other metastable crystal phases. It is an irreversible process. It is generally believed that the metastable o-phase should be transformed from another metastable t-phase because of the structural similarities, and the application of anisotropic stress is one of the keys to this transition. Common HfO2 ferroelectric layer formation processes such as doping, surface energy effect, island coalescence, thermal expansion mismatch, metal capping layer and oxygen vacancies are all related to anisotropic stress[6]. Figure 3 shows the evolution of each HfO2 crystal phase and crystal structure during different processes[7].

Figure 3. The Evolution of Each Crystal Phase and Crystal Structure of HfO2 Film During Different Processes[7]

The mechanism behind the formation of o-phase HfO₂ films can also be explained using the kinetic model as shown in Figure 4[8]. Taking Zr doped HfO₂ films (Hf_0.5Zr_0.5O₂, HZO) as the example, the change in the crystal phase during the tempering process can be divided into four stages:

1. Initial Stage: As deposited fluorite-structured films have extremely tiny nuclei (a radius of about 2 nm), it is likely to exist in the form of o-phase nanocrystallities.
2. Heating Stage: Since the t-phase has a lower entropy than o-phase/m-phase, its free energy will drop. Therefore, the stable phase of the film at this stage changes from o-phase to t-phase.
3. Holding Stage: The free energy of the m-phase will decrease. According to the law of thermal dynamics, the film should therefore tend toward forming the m-phase. However, because the t-phase and m-phase energy barrier can be as high as 250meV/formula unit (f.u.), the film will remain in the t-phase at this stage. However, higher annealing temperatures and a longer annealing time may enable the system to have energy beyond this energy barrier, causing the film to form the m-phase.
4. Cooling Phase: Since the energy barrier between the t-phase and o-phase is only 30 meV/f.u., there is a good chance that the film will form the second stable o-phase rather than the most stable m-phase.

Figure 4. Phase Diagram of Zr Doped HfO2 Film During Annealing[8]

To facilitate the film to form the o-phase, it is necessary to reduce the free energy of the o-phase. As shown in Figure 5, increasing the cooling rate (τ) in the annealing process is beneficial to increasing the proportion of o-phase in the film[9]. Recent studies have reported that the Pr and Ec of HfO2 ferroelectric thin films can reach 50μC/cm2 and 4.75MV/cm respectively through fast quenching with water. This far exceeds the results of typical rapid thermal annealing processes[10].   Figure 5. The Relationship Between the Cooling Rate and the Thin Film’s Crystal Phase[9]

The ferroelectric materials used in memory are divided mainly into three types of memory cell structures. As shown in Figure 6, these include:

Figure 6. Schematic Diagrams of Ferroelectric Memories with Different Structures and the Corresponding Read Currents[11]

(a) FeRAM: Ferroelectric RAM is comprised of a transistor and a ferroelectric capacitor (b) FeFET: The single transistor form of ferroelectric FET (c) FTJ: A ferroelectric tunnel junction with upper/lower electrodes sandwiching the ferroelectric film[11]

Ferroelectric layers with perovskite structures such as BTO and PZT were proposed as early as the 1940s and 50s. It was a master’s student at MIT who first proposed using BTO ferroelectric capacitors as data storage components in his thesis in 1952. This can be regarded as a prototype of FeRAM. As shown in Figure 6(a), the FeRAM memory cell is composed of a transistor and a ferroelectric capacitor. This structure is similar to that of the mainstream DRAM memory cell. The ferroelectric capacitor is composed of a metal upper electrode/ferroelectric material/metal lower electrode. In this memory cell structure, the lower electrode voltage of the ferroelectric capacitor is controlled by the bit line (BL) through the transistor, whereas the upper electrode voltage is determined by the plate line (PL). The direction of the electric dipole in the ferroelectric capacitor can be changed by the voltage polarity and difference between the upper and lower electrodes.

Let us assume that the up direction for the electric dipole is logic ”1” and down is logic ”0”. Then, to write logic ”0” data to the ferroelectric capacitor, we would apply 0V and a high voltage (such as Vcc) to the BL and PL respectively while the transistor is on. Otherwise, logic ”1” data can be written. To read data, 0V and Vcc can be applied to the BL and PL respectively. If the data stored in the ferroelectric capacitor is a logic ”1”, then the electric dipole will change direction and become a logic ”0” and generate a dipole switching current, which will then charge the BL, raising the BL voltage. Conversely, if the data stored in the ferroelectric capacitor is a logic ”0”, the direction of the electric dipole remains the same, and the BL voltage changes very little. By measuring the high and low values of the BL voltage, it is possible to determine whether the data stored in the ferroelectric capacitor is logic ”1” or logic ”0”. However, regardless of what kind of data was originally stored, once it undergoes the reading process, all the data will be converted into logic ”0”. As such, this is a kind of destructive reading. Therefore, the correct data must be written in again after the data is read.

Commercial FeRAM memory devices based on PZT ferroelectric materials have writing speeds in the tens of nanoseconds (ns) and up to 10 years of data retention. Additionally, the repeated operation endurance can be as high as 10¹⁵ times. It is worth noting that the data retention capabilities of ferroelectric capacitors are closely related to the size of the depolarization field. Under ideal conditions, when the ferroelectric layer is polarized, the induced charge Q on the electrode can completely compensate for the polarization P in the ferroelectric layer. In this case, the electric field inside the ferroelectric layer would be zero. However, actual electrodes are not ideal conductors. The results will be in an imbalance between Q and P and induced an electric field within the ferroelectric layer. This is the depolarizing electric field. The larger the depolarization field, the more the polarization in the ferroelectric field to decay over time, resulting in the deterioration of the component’s ability to preserve polarization. Depolarization fields are inevitable. Fortunately, the ferroelectric capacitor of FeRAM memory uses metal electrodes, which have a relatively small depolarization field, so excellent data retention can still be achieved.

If FeRAM is fabricated with an HfO₂ ferroelectric layer instead of a PZT ferroelectric layer, it will have a higher Ec and be more resistant to the effects of depolarizing electric fields. Compared to DRAM, FeRAM relies on the electric dipole orientation of the ferroelectric layer to store data. This means that, unlike DRAM, which stores data with electric charge, there are no charge drain issues. Therefore, there is no need for periodic data updates (refreshing). Since the storage of data is independent of charge, there is greater immunity to radiation-induced currents and possible data destruction. As such, it is often used in the electronic equipment required for space missions and nuclear medical instruments. In addition, FeRAM is considered a non-volatile memory. Its properties and characteristics are considerably different from those of DRAM Volatile memory. After years of development, the FeRAM memory market has undergone many changes. In 1992, Ramtron began to sell commercial FeRAM. In 2011, Texas Instruments released the first FeRAM-based microprocessor. By 2012, Cypress had acquired Ramtron, and, in 2020, Infineon purchased Cypress. Since then, FeRAM has also become one of the memory technologies used by Infineon in its automotive electronics. Currently, Infineon’s largest FeRAM chip is 16Mbit and still uses PZT ferroelectric materials.

The difference in the Vt corresponding to logic ”1” or ”0” is called the memory window (MW). The larger the memory window, the easier it is to tell the difference between a logic ”1” and ”0” [12]. When a memory cell only stores 2 Vt states (such as a logic ”1” and ”0”), it means that it can store 1 bit of data. If the memory window increases, it would mean that other states could be tolerated within this range. If 4 Vt states can be distinguished, then 2 bits could be stored. At present, existing literature reports that FeFET memory can store 3 bits[13].

The degree of steering of the electric dipole in FeFET memory can be adjusted via different gate voltages. This in turn controls the number of carriers in the channel, which helps realize the goal of achieving different Vts. This method of storing 2 or 3 bits in a single memory cell is similar to the concepts of the Multi Level Cell (MLC) and the Triple Level Cell (TLC) of NAND Flash memory technology. It can reduce manufacturing costs and greatly increase memory density. To achieve the goal of single memory cell multi-bit storage, it is essential to improve the memory window.

The structure of FTJ memory is relatively simple. As shown in Figure 6(c), it is a sandwich structure in which the ferroelectric layer lies between the upper and lower electrodes. The barrier height can be adjusted via the polarization direction of the ferroelectric layer. Due to the exponential function relationship between the tunneling current and the energy barrier height, you can adjust the tunneling current to induce tunneling electroresistance (TER), thus forming a switch between high resistance and low resistance.

So far, most reported FTJ memories can operate at voltages below 4V and have an operating speed of between 10 to 100ns. As such, they have significant advantages over traditional Flash in terms of low write power consumption and non-destructive reading. In addition, FTJ memory’s high/low resistance ratio (TER ratio) or ON/OFF ratio is about 10~100. Generally, increasing the thickness of the ferroelectric layer helps to increase the TER ratio. However, doing so reduces the on current and the read current, which increases reading time. Another more feasible solution is to use a double-layer structure that includes a ferroelectric layer and an interface layer and make the electric dipole switching and the tunneling current occur in different films.

FTJ memory is still in a very early stage of development. It has great potential to become the memory technology of the next generation, but, at this stage, its low current density limits the speed at which data can be read. In addition, the suppression of the sneak current under the array structure and the correlation analysis of the statistical distribution of high/low resistances require further study. Therefore, FTJ is currently more suitable for performing a large number of parallel operations in In-Memory Computing[11].

Figure 9. FeRAM Memory Endurance[15]

Figure 9 is a graph showing the relationship between the polarization of the ferroelectric capacitor component (TiN/HfO2 ferroelectric layer/TiN) and the number of operations (endurance) of a typical FeRAM memory. It can be clearly observed that the polarization increases with the number of operations (wake-up effect) and then gradually deteriorates (fatigue effect). The total number of times the ferroelectric capacitor can operate is limited by the breakdown of the ferroelectric layer[15-16].

The wake-up and fatigue effects can cause the misinterpretation of data, so it is necessary to suppress these effects as much as possible. It is generally believed that wake-up is the redistribution of the initial oxygen vacancy pinning the ferroelectric domain wall (domain wall pinning) by obtaining energy through repeated operation. The redistribution increases with the number of operations. In turn, the pinning phenomenon is relieved or the crystal phase of the ferroelectric layer at the interface is transformed from the t-phase to the o-phase.

As for fatigue, it comes from the oxygen vacancies generated by the TiOx at the TiN electrode/HfO2 ferroelectric layer interface under repeated operation causing charge trapping. As shown in Figure 10, these trapped charges may form new electric dipoles and lead to ferroelectric domain wall pinning[15]. Breakdown is also related to the continuous accumulation of oxygen vacancies, which form a permanent leakage path[17].

Figure 10. Schematic Diagram of Domain Wall Pinning in the Ferroelectric Layer[15]

Suppressing possible reactions in the interfaces between the metal electrodes and the HfO₂ ferroelectric layer is the key to reducing oxygen vacancies[16]. It has been pointed out in the literature that interface reactions can be effectively suppressed using the appropriate NH₃ plasma nitridation treatment after the metal electrode deposition and before the HfO₂ ferroelectric layer deposition so that the device is free from wake up and fatigue effects [18]. Another way to extend the endurance of ferroelectric memory is to slow down the breakdown effect.

The information in Figure 2 tells us that the Ec of the HfO₂ ferroelectric layer is several times higher than that of the traditional calcium ore ferroelectric layer. This is beneficial to countering depolarizing electric fields and improving the memory window of FeFET memory. However, the Ec of the HfO₂ ferroelectric layer can reach up to 50% of the breakdown field (E_BD). In contrast, the Ec/E_BD ratio of PZT is only 10% at most. This parameter means that the HfO₂ ferroelectric layer operates with an electric field that is closer to collapse. Therefore, its endurance is not as good as that of ferroelectric memory using PZT. One feasible way to extend the number of operations is to reduce the Ec of the HfO₂ ferroelectric layer. It has been reported in the literature that the incorporation of La into the Hf_0.5Zr_0.5O₂ ferroelectric layer can reduce the Ec, allowing endurance to reach 10¹¹ times. This is the best endurance performance for large area (2000μm²) ferroelectric capacitors [19]. Doping HfO₂ with Si is another process that can reduce the Ec of the ferroelectric layer. By reducing the area of the capacitor to 28μm², the defect density becomes more manageable and endurance can be expected to reach 10¹² times[20].

In addition, some research teams have proposed using antiferroelectric materials that with the imprint effect (the phenomenon of +Ec/-Ec asymmetry brought about by a built-in electric field) to reduce the operating voltage of the device. Research shows that this can enable endurance to exceed 10¹⁰ times[18]. As antiferroelectric materials can be realized by adjusting the proportion of Zr doping in HfO₂ films, it is also compatible with existing processes, so it is a research direction worth investing in. However, to integrate FeRAM into random access memory applications, endurance must reach at least 10¹⁵ times, so there is still much room for improvement.

Figure 11 shows the main ways to improve endurance from the perspectives of process and structure. As shown in Figure 11(a), taking a silicon semiconductor substrate as an example, the dielectric constant of the HfO₂ ferroelectric layer is increased to 25 due to crystallization into a ferroelectric phase during the annealing process, and a SiO_x interface layer with a dielectric constant of 3.9 will be generated between the HfO₂/Si layers.

For the necessary properties to maintain continuity according to the electric displacement field, the ferroelectric layer electric field (E_F) and the interface layer electric field (E_IL) need to satisfy the following relationship. This relationship also means that the larger the saturation polarization value (Ps) of the ferroelectric layer, the higher the electric field that the IL will be subjected to, which is not good for endurance[22]. Estimated with an E_F approximately equal to the Ec (1MV/cm), when Ps is greater than 5μC/cm², the E_IL will be greater than 20MV/cm. The larger the polarization, the larger the E_IL, and it then closer to the collapse of the electric field of the interface layer. Therefore, the endurance of FeFET memory is usually not determined by the ferroelectric layer itself but by the limitations of the interface layer[22-24].

Figure 11.　Schematic Diagram of FeFET Memory with Different Oxide Layer Stack Structures[22]

Under different gate bias polarities, the high electric field of the SiO_x interface layer can lead to the easy injection of charges from the gate metal or silicon channel, so repeated operations can cause interfacial trap generation or charge trapping effects. The former causes sub-Vt swing degradation in FeFET memory devices. The latter causes a shift in Vt. Both will reduce the memory window, which is not conducive to the continuous operation of the component[25]. As shown in Figure 11(b), growing high-k interface layers and lowering the E_IL is one possible way to reduce the negative effects of charge injection.

Figure 12. TEM Image of the High Dielectric Constant of the AlON Interface Layer[26]

As shown in Figure 12, introducing an AlON interface layer with a dielectric constant of 9 can effectively suppress charge injection because the EIL is reduced. Therefore, it can operate at high voltages (±5V) and has an endurance of up to 105 times under long time pulse (10-4s) operation. Increasing the electric field of the ferroelectric layer will also allow the electric dipole to be converted more efficiently. Therefore, a memory window of up to 3.1V can be obtained at ±4V [26]. The literature on SiNx as an interface layer discusses a similar concept. At low voltages (±3V), the endurance is an excellent 1010 times under short time pulse (250ns) operation[27]. As shown in Figure 13, the introduction of an epitaxial SiGe channel can also improve endurance by improving the quality of the interface layer[28].

Figure 13. Properties of Ferroelectric Thin Film Interfaces on SiGe Substrates[28]

Figure 14. Endurance of FeFET Memory with Different Channel Types[29]   In addition, though most FeFET memories focus on n-type channels, recent studies have found that the number of hot electrons induced holes in p-type channels is more moderate as shown in Figure 14. Therefore, p-type channels have better endurance performance[29].

As shown in Figure 11(c), if metal is deposited between the ferroelectric layer and the interface layer of FeFET memory to form a metal/ferroelectric layer/metal/interface layer/semiconductor device structure, then the metal/ferroelectric layer/metal can be regarded as a ferroelectric capacitor. As ferroelectric capacitors enjoy relatively excellent endurance, this structure can improve the endurance of the component. In addition, the surface area of the upper metal/ferroelectric layer/metal (S_F) part and the area of the lower metal/interface layer/semiconductor (S_I) part of the structure can be adjusted respectively so that the ratio of S_I/S_F is greater than 1. The purpose of this is to make the capacitance value of the upper half smaller than the capacitance value of the lower half so that most of the voltage will fall on the ferroelectric layer, thus reducing the voltage drop of the interface layer in order to reduce the negative effects of charge injection and increase the memory window.

Furthermore, as shown in Figure 11(d), the upper half of the ferroelectric capacitor element and the lower half of the transistor element of the aforementioned memory structure can be completed in the back-end and front-end processes respectively. This structure not only improves reliability but also allows the thermal process to be adjusted separately[30]. However, the lower electrode of the ferroelectric capacitor element plays a role similar to that of a floating gate. The excessive leakage current or repeated operations may cause the floating gate to accumulate too much charge that cannot be eliminated, leading to over screen polarization of the ferroelectric layer. This prevents the memory device from functioning normally. Therefore, everything from the material selection to the thicknesses of the structure need to be carefully designed[22].

The discovery of HfO₂ ferroelectric materials has opened new paths for the development of FeRAM, FeFET and FTJ memory technology. A decade of diligent work by numerous top research teams and the incorporation of innovative materials, processes and structures have led to many significant improvements in the fields of FeRAM and FeFET memory, especially in areas such as low power consumption/high speed operation, data retention and reliability under repeated operations. Figure 15 is a comparison of important parameters of various emerging memories[31]. Ferroelectric memory is extremely competitive, and its performance in all aspects is expected to continue to improve.

In the future, it will be necessary to overcome the problem of the device-to-device variation of polycrystalline ferroelectric films when scaling down or the characteristics variability in repeated cycle-to-cycle operation of the same device in order to meet the needs of large-scale memory array operations. When scaling down, the number of grains in each component is reduced. Characteristics such as the size of these grains, the crystal phase distribution (ferroelectric/non-ferroelectric phase ratio), the orientation, and grain boundaries can all vary. Therefore, the variability between components will become more and more obvious as they are scaled down[23]. As such, the identification and advanced physical analysis of material microstructures will become more and more important. One approach to improving variability is to reduce the grain size to 2-3nm while maintaining ferroelectricity. This allows for the inclusion of hundreds of grains in a miniaturized component and allows for non-uniformities to be averaged out due to the larger number of grains. Grain size can be adjusted by controlling the thermal process during the growth of the HfO₂ ferroelectric layer. Increasing the cooling rate, for instance, is one way to achieve a smaller grain size[10].

Figure 15. Table Comparing the Characteristics and Parameters of Emerging Memories and Existing Flash Memory[31]

The endurance of FeRAM memory based on HfO₂ ferroelectric materials is expected to reach 10¹² times. Though there is a distinct gap between that and the 10¹⁵ times of commercial FeRAM memory based on PZT ferroelectric materials, continued efforts in research and development are expected to narrow that gap. HfO₂-based FeRAM memory will see further developments in the future not only in the areas of component miniaturization and the realization of three-dimensional structures[32] but also the development of multi-bit storage[33-34]. Though the structure of FeRAM is similar to that of DRAM, the high polarization density mean that its memory cells can shrink more efficiently. Therefore, it has more advantages in terms of process complexity and costs[11].

FeFET memory based on HfO₂ ferroelectric materials was initially positioned in the market as an embedded nonvolatile memory[35] for assisting computing functions. FeFET memory has several advantages over existing embedded flash memory, including high-speed, low-voltage operation, the fact that it does not need to have a charge pumping circuit specially designed to help control the wordline, and more. Therefore, it has the potential to eventually replace embedded Flash memory.

In the long run, it also has great potential in the standalone memory market for high-density storage applications as the technology for storing 3 bits in a single memory cell has been realized[13], and the vertical FeFET memory device structure similar to that of 3D NAND Flash memory has also been successfully demonstrated[36-37]. There are many possibilities to be found through the proper integration of this technology. In addition, FeFET memory can play the roles of both synapses [38-39] and neurons [40-41] in neuromorphic computing systems. As such, it is a memory technology with great potential in the future of In-Memory Computing architectures.

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In truth, ferroelectric memory technology has been under development for more than fifty years. Since its driving principle is the use of voltage instead of current to change the state of bits, its power consumption for reading and writing is extremely low. At the same time, these devices are non-volatile, durable, and have ultra-fast switching speeds, so they have always been regarded as ideal for storage applications. However, most early ferroelectric memories were fabricated based on lead zirconate titanate (PZT) of the perovskite family. The complex piezoelectric properties of these materials and their difficulties with conformal deposition limited these products to niche markets. However, in recent years, HfO₂, a common semiconductor material, has been found to have ferroelectric properties. This material’s application process is relatively simple, making it more cost-efficient. It has inspired a new wave of industrial development opportunities for ferroelectric memory.

The semiconductor industry continues to move towards smaller process nodes, and DRAM and NAND Flash are beginning to face the severe technical challenges of scaling down. Ferroelectric memory based on HfO₂ ferroelectric materials not only has more room for miniaturization but also has the potential for 3D structure integration and even multi-bit storage. In addition, as a capacitive element based on the principle of spontaneous polarization, ferroelectric memory is not only reliable and non-volatile but also has extremely fast reading and writing speeds and features such as high durability for repeated access and ultra-low power consumption. It also possesses advantages in terms of process complexity and cost. As such, it has an excellent chance at becoming the emerging storage solution of the post Moore’s Law era. However, to take the lead in the ferroelectric memory industry, it will not be enough merely to seek out advantages in component innovation technology. The related circuits and system packaging integration technology will also be key. We hope that the domestic industry, government and academia will work together to develop a comprehensive strategy for grasping this incredible opportunity as soon as possible.

This article provided a comprehensive introduction to the development of ferroelectric memory. It also clearly articulated the technical challenges and opportunities facing this technology. We hope that it has helped you understand this truly promising technology. Professor Wu of Tsing Hua University has devoted himself to the academic research of ferroelectric memory for many years. His team has published many important research studies. Their work has been published in renowned international journals. Their work was even chosen to be the cover and editors’ pick of last year’s IEEE Electron Device Letters. MA-tek is very honored to join hands with Professor Wu to carry out industry-university cooperations this year by providing all the analysis services necessary for ferroelectric memory research. MA-tek has a comprehensive set of testing equipment and the professional technical experience to fully meet the various analysis and testing needs of advanced semiconductor processes and packaging.