[MAFT 2026 | H2 Technology Seminar] "Crystal" Moving into the Future: The Next Wave of Technological Revolution from Memory, Silicon Photonics to Quantum Computing

National Yang Ming Chiao Tung University

Professor Ko Ming-Tao

Tsinghua University

Professor Chen Can-yao

National Taiwan University

Professor Liu Zhiwei

Poster Exhibition and Discussion

Lunch gathering

Afternoon - MAFT Seminar(In-person/Online Event)

Check-in

Opening

Tsinghua University

Professor Wu Yong-Hsien

Topic: From Radiation Resistance Challenges to Reliability Design: Development Opportunities for Ferroelectric Memory in Future Space Electronics

With the rapid development of low Earth orbit satellites, Space Edge Computing, and Agentic AI, the demand for high-performance, low-power, and radiation-hardened non-volatile memory in future space systems is increasing. Compared to traditional flash memory that stores data using charge, ferroelectric field-effect transistor memory (FeFET) uses the direction of ferroelectric polarization as the information carrier, offering advantages such as low voltage operation, non-destructive reading, and excellent radiation resistance potential. Therefore, it is regarded as an important candidate technology for the next generation of space electronics and intelligent computing systems.

This presentation will first introduce the main damage mechanisms of radiation on semiconductor devices, including total ionizing dose (TID), single event effects (SEE), and reliability issues caused by oxygen vacancies and interface defects. It will then explain the development history of radiation-resistant ferroelectric memory based on HfO₂ and share the systematic results of our research team's recent studies on HfZrOₓ (HZO) FeFET radiation resistance, including interface engineering (AlON interface layer), channel engineering (p-type and Ge channels), ferroelectric material composition engineering (Zr concentration optimization and composition gradient HZO), and high-energy proton radiation verification. At the same time, this presentation will also introduce the innovative superlattice + solid solution stacked structure developed in collaboration with MA-tek, and further explore its application potential in radiation-resistant ferroelectric memory, highlighting the critical role of advanced material analysis, process structure design, and defect engineering in next-generation reliability engineering, as well as the importance of establishing a radiation-resistant memory design framework.

Finally, from the perspective of future applications, we will explore the development potential of ferroelectric memory in application scenarios such as autonomous satellite systems, space edge computing, and future Space Data Centers.

National Yang Ming Chiao Tung University

Professor Hong Ruihua

This topic covers a comprehensive analysis from technological drivers, core packaging evolution, heterogeneous integration methods to the industrial ecosystem.

1. Technological Driving Force: The Transmission Revolution Brought by AI/ML

• Background of Demand: With the rise of AI and machine learning (ML), the data exchange volume within data centers has increased significantly, and traditional electrical signal transmission is facing bottlenecks in bandwidth and latency.
• Solution: Technological evolution has prompted the internal data centers to replace electrical signals with optical signals for transmission and exchange, in order to meet the demands of ultra-high performance computing.

2. The evolution of packaging architecture: from plug-in to Co-Packaged Optics (CPO)

• Traditional architecture: Pluggable Transceiver places the optical engine on the PCB carrier board. Although the technology is mature, the transmission path is relatively long.
• Advanced Architecture (CPO): Directly designing the optical engine on the IC substrate, packaging the PIC (Photonic Integrated Circuit) together with the EIC (Electronic Integrated Circuit) through advanced packaging.

• CPO 1.0: The transmission rate is approximately 100 Gb/s, mainly using 2D/2.5D packaging, and the laser light source is external (ELS).
• CPO 2.0: The transmission rate is increased to over 200 Gb/s, using 2.5D/3D packaging, with lasers embedded in the PIC chip, which can reduce the module area by more than 30%.

3. Core Integration Technology: Silicon Photonics and Heterogeneous Integration

• Comparison of integration solutions: The source compares three architectures: Pure Silicon, Indium Phosphide (InP), and Hybrid.

• Heterogeneous integration is regarded as the best path for "complementing strengths and compensating for weaknesses," achieving high component integration, small size, and medium to low cost.

• Integration Method:

• Heterogeneous Integration: Combining materials and then proceeding with component processing (such as Die to wafer bonding).
• Hybrid Integration: Components are integrated after each is completed (e.g., Flip-chip integration).

4. Emerging Interconnect Technology Applications

• Micro LED interconnect: Aimed at short-distance transmission for Chip-to-Chip or board-to-board, expected to mature between 2027-2030, pursuing ultra-low energy consumption (< 1pJ/bit).
• VCSEL interconnect: mainly used for high-speed data exchange from rack to rack.

5. Industry Ecosystem and Prototyping Platform

• Supply chain layout: It covers domestic and foreign manufacturers from ASIC chip, silicon photonic chip design and manufacturing, to packaging testing and system substrates.
• ITRI Pilot Manufacturing Platform: The Industrial Technology Research Institute has established a pilot manufacturing platform for III-V integrated photonic chips, aiming to lower the technical barriers for manufacturers entering the development of photonic chips and to address the lack of an open platform for 8-12 inch semiconductors.

6. Patent Distribution and Technology Validation

• Patent Status: The Industrial Technology Research Institute has laid out 22 cases and 39 patents in the field of silicon photonics, covering core technologies such as components, packaging, and testing.
• Verification measurement: Currently equipped with a fully automated measurement platform with a capacity of 224 Gb/s, aiming to achieve a measurement capability of 448 Gb/s by 2027.

Networking & Break

National Cheng Kung University

Professor Liu Quanpu

Topic:Advanced Packaging and Electromagnetic Protection Materials in the 6G Era

With the rapid evolution of autonomous vehicle technology, vehicles are no longer just a means of transportation, but have become highly intelligent mobile platforms. From sensors to control units, from communication modules to artificial intelligence (AI) chips, every automotive module plays an indispensable role. In this technological revolution, "module verification" has become a key link to ensure safety, stability, and reliability.

At present, automotive module verification is divided into two main categories within the AEC-Q verification family: Multichip Module (MCM) and Optoelectronic Multichip Module (OE-MCM), referring to standards such as AEC-Q104 and AEC-Q102-003. The verification framework is divided into general commonality verification and special verification. Due to the wide variety of automotive module types, there are often issues with the applicability of certain test items. Therefore, it is essential to have a professional verification experience like that of MA-tek to tailor verification solutions that meet the standards, allowing automotive modules to quickly and confidently enter the new era of intelligent driving!

National Yang Ming Chiao Tung University

Professor Li Pei-wen

Topic:Material Defined Germanium Quantum-dots for High Performance Quantum Computing

The holy grail for implementing semiconductor quantum computing hardware is to take full advantage of robust CMOS manufacturing technology and operate at benign environment. Motivation to use Si/Ge quantum-dots (QDs) for implementing CMOS-integrable qubits and their charge/photon sensors is strong in light of the advanced CMOS and Si photonics technology, which allows full integration of qubits with CMOS control/readout circuitry and is beneficial to facilitate progress toward large-scale quantum computers. Remarkable achievements have been realized on Si/Ge spin qubits by forming fine metal-gates over Si/Ge or Si-MOS quantum-well structures. However, Si/Ge gate-defined spin qubit operation is limited at milli-Kelvin temperatures due to the challenge in forming sufficiently high potential barriers separating the Si/Ge QDs. On the other hand, material-defined QDs promise higher temperature operation and better immunity to quantum leakage. However, the holistic device and technology co-design of QDs, barriers, and control gates all in nm-scale is a formidable task. Another technical challenge lies in detecting minuscule signal of quantum states due to strong charge confinement wherein.
Starting with our exciting discovery of Ge spherical quantum dot (QD) formation via the peculiar and symbiotic interactions of Si, Ge and O interstitials, we have embarked on an exciting journey of vigorous exploration, creating unique configurations of self-organized Ge QDs/Si-based barrier layers. Our aim is to generate advanced Ge QD qubit and photonic devices using standard, mainstream Si processing techniques. This talk summarizes our portfolio of innovative Ge QD configurations. With emphasis on both controllability and repeatability, we have fabricated size-tunable, spherical Ge QDs that are placed at predetermined spatial locations within Si-containing layers (SiO2, Si3N4, and Si) using a coordinated combination of lithographic patterning and self-assembled growth. A significant engineering advantage of our approach is the high-temperature thermal stability of Ge QDs that are formed by thermal oxidation of poly-SiGe at 900 oC, offering process flexibility in engineering confinement barriers and nanoelectrodes for quantum electronics (qubits and single-charge sensing) as well as in waveguide-material choices and meta-surface designs for quantum photonics (light emitters and photodetectors). We have demonstrated steady-state operation of Ge-DQDs and single-hole transistors (SHTs) in few-charge regime at T > 10 K. Our Ge QD configurations also allow a myriad of integration possibilities including SiN-waveguided Ge-QD photodetectors and light-emitters for optical interconnects and few-photon detections for trapped ion qubits.

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